PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Özkaya, Ilter"

Author of the publication

copydeleteadd this publication to your clipboard
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS.

, , , , , , , , , , , and . J. Solid-State Circuits, 53 (4): 1214-1226 (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ilter Ünal University of Stuttgart

 

Other publications of authors with the same name

A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 53 (11): 3268-3279 (2018)A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET., , , , , , , , , and 1 other author(s). ISSCC, page 112-114. IEEE, (2019)Design considerations for 50G+ backplane links., , , , , , , , , and 1 other author(s). ESSCIRC, page 477-482. IEEE, (2016)A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET., , , , , , , , , and . J. Solid-State Circuits, 53 (12): 3508-3516 (2018)A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration., , , , , , , , , and . VLSI Circuits, page 275-276. IEEE, (2018)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 53 (4): 1227-1237 (2018)A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 52 (12): 3458-3473 (2017)A 50V input range 14bit 250kS/s ADC with 97.8dB SFDR and 80.2dB SNR., , , , and . ESSCIRC, page 71-74. IEEE, (2014)A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE., , , , , , , , , and . VLSI Circuits, page 267-268. IEEE, (2018)