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B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE.

P. Francese, A. Cevrero, I. Özkaya, M. Brändli, C. Menolfi, T. Morf, M. Kossel, L. Kull, D. Luu, and T. Toifl. VLSI Circuits, page 267-268. IEEE, (2018)

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A parallelized layered QC-LDPC decoder for IEEE 802.11ad.A. Balatsoukas-Stimming, N. Preyss, A. Cevrero, A. Burg, and C. Roth. NEWCAS, page 1-4. IEEE, (2013)Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors.G. Beanato, A. Cevrero, G. Micheli, and Y. Leblebici. Microelectronics Journal, (2016)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.G. Kim, L. Kull, D. Luu, M. Braendli, C. Menolfi, P. Francese, H. Yueksel, C. Aprile, T. Morf, M. Kossel and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET.I. Özkaya, A. Cevrero, P. Francese, C. Menolfi, T. Morf, M. Braendli, D. Kuchta, L. Kull, C. Baks, J. Proesel and 7 other author(s). J. Solid-State Circuits, 53 (4): 1227-1237 (2018)A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET.I. Özkaya, A. Cevrero, P. Francese, C. Menolfi, T. Morf, M. Braendli, D. Kuchta, L. Kull, C. Baks, J. Proesel and 7 other author(s). J. Solid-State Circuits, 52 (12): 3458-3473 (2017)3D configuration caching for 2D FPGAs.A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, P. Brisk, Y. Leblebici, P. Ienne, and M. Skerlj. FPGA, page 286. ACM, (2009)Using 3D integration technology to realize multi-context FPGAs.A. Cevrero, P. Athanasopoulos, H. Parandeh-Afshar, M. Skerlj, P. Brisk, Y. Leblebici, and P. Ienne. FPL, page 507-510. IEEE, (2009)A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS.T. Toifl, C. Menolfi, M. Brändli, A. Cevrero, P. Francese, M. Kossel, L. Kull, D. Luu, T. Morf, and I. Özkaya. VLSI Circuits, page 53-54. IEEE, (2018)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver.G. Kim, L. Kull, D. Luu, M. Braendli, C. Menolfi, P. Francese, C. Aprile, T. Morf, M. Kossel, A. Cevrero and 3 other author(s). ISCAS, page 1-5. IEEE, (2018)A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.G. Kim, M. Kossel, A. Cevrero, I. Özkaya, A. Burg, T. Toifl, Y. Leblebici, L. Kull, D. Luu, M. Braendli and 5 other author(s). J. Solid-State Circuits, 55 (1): 38-48 (2020)

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A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE.

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A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE.