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Disambiguation of "Toifl, Thomas"

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A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE.

, , , , , , , , , and . VLSI Circuits, page 267-268. IEEE, (2018)

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Dipl.-Ing. Thomas Kuestner

Scan time reduction in DWI of the pancreas using simultaneous multislice technique with different acceleration factors: how fast can we go?, , , , , , , and . Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)

apl. Prof. Dr. Thomas Sottmann University of Stuttgart

Data for 'Adjustable polystyrene nanoparticle templates for the production of mesoporous foams and ZnO inverse opals', , , , , and . Dataset, (2024)Related to: Abitaev, Karina; Qawasmi, Yaseen; Atanasova, Petia; Dargel, Carina; Bill, Joachim; Hellweg, Thomas; Sottmann, Thomas: Adjustable polystyrene nanoparticle templates for the production of mesoporous foams and ZnO inverse opals. In: Colloid and Polymer Science 299 (2021), 243-258. doi: 10.1007/s00396-020-04791-5.

Univ. -Prof. Dr. Thomas Graf University of Stuttgart

Synchrotron X-ray video of full-penetration laser welding of aluminum AA1050A, , , , , , and . Dataset, (2024)

Thomas Maier

Thomas Maier

 

Other publications of authors with the same name

Active compensation of supply noise for a 5-GHz VCO in 45-nm CMOS SOI technology., and . ISCAS, page 2617-2620. IEEE, (2008)A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS., , , , , , and . ISSCC, page 152-154. IEEE, (2011)A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS., , , , , , , , , and 2 other author(s). ESSCIRC, page 148-151. IEEE, (2015)High-speed link with trellis-coded modulation and Reed-Solomon coding., , , , , and . CSCN, page 231-236. IEEE, (2016)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology., , , , , , , , , and 11 other author(s). ISSCC, page 324-326. IEEE, (2012)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 53 (4): 1227-1237 (2018)A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 52 (12): 3458-3473 (2017)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS., , , , , , , , and . J. Solid-State Circuits, 48 (12): 3268-3284 (2013)