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Design optimization of polyphase digital down converters for extremely high frequency wireless communications., , and . VLSI-SoC, page 207-212. IEEE, (2015)Direct Reconstruction of Saturated Samples in Band-Limited OFDM Signals., , , , and . CoRR, (2018)A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces., , , and . IEEE Trans. on Circuits and Systems, 63-II (12): 1126-1130 (2016)Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)., , , , and . FPGA, page 262. ACM, (2015)Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link., , , , and . MWSCAS, page 1147-1150. IEEE, (2019)Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data links., and . APCCAS, page 164-167. IEEE, (2016)Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme., , , , and . IEEE Trans. on Circuits and Systems, 64-I (12): 3192-3201 (2017)A Study on the Programming Structures for RRAM-Based FPGA Architectures., , , and . IEEE Trans. on Circuits and Systems, 63-I (4): 503-516 (2016)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links., , , , and . IEEE Trans. on Circuits and Systems, 64-II (12): 1387-1391 (2017)