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Disambiguation of "Yueksel, Hazar"

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A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.

, , , , , , , , , , , , , , and . ISSCC, page 476-478. IEEE, (2019)

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Other publications of authors with the same name

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 55 (1): 38-48 (2020)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders., , , , , , , , , and 3 other author(s). IEEE Trans. on Circuits and Systems, 65-I (10): 3529-3542 (2018)10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS., , , , , , , , , and 4 other author(s). VLSIC, page 228-. IEEE, (2015)A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 53 (11): 3268-3279 (2018)A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS., , , , , , , , , and 2 other author(s). ESSCIRC, page 148-151. IEEE, (2015)High-speed link with trellis-coded modulation and Reed-Solomon coding., , , , , and . CSCN, page 231-236. IEEE, (2016)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)Design considerations for 50G+ backplane links., , , , , , , , , and 1 other author(s). ESSCIRC, page 477-482. IEEE, (2016)