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Disambiguation of "Aprile, Cosimo"

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A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.

, , , , , , , , , , , , , , and . ISSCC, page 476-478. IEEE, (2019)

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Cosimo Gregucci University of Stuttgart

 

Other publications of authors with the same name

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants., , , , , , , , and . IEEE Trans. on Circuits and Systems, 65-I (11): 3929-3941 (2018)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver., , , , , , , , , and 3 other author(s). ISCAS, page 1-5. IEEE, (2018)A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 55 (1): 38-48 (2020)DCT Learning-Based Hardware Design for Neural Signal Acquisition Systems., , , , and . Conf. Computing Frontiers, page 391-394. ACM, (2017)Real-Time DCT Learning-based Reconstruction of Neural Signals., , and . EUSIPCO, page 1925-1929. IEEE, (2018)A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS., , , , , , , , , and 4 other author(s). VLSIC, page 228-. IEEE, (2015)Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition., , , , , , and . ACM Great Lakes Symposium on VLSI, page 433-438. ACM, (2016)A primal-dual framework for mixtures of regularizers., , , , and . EUSIPCO, page 240-244. IEEE, (2015)Structured sampling and recovery of iEEG signals., , , , and . CAMSAP, page 269-272. IEEE, (2015)