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Disambiguation of "Morf, Thomas"

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A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE.

, , , , , , , , , and . VLSI Circuits, page 267-268. IEEE, (2018)

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Dipl.-Ing. Thomas Kuestner

Scan time reduction in DWI of the pancreas using simultaneous multislice technique with different acceleration factors: how fast can we go?, , , , , , , and . Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)

Thomas Maier

Thomas Maier

Thomas Maier

Thomas Maier

 

Other publications of authors with the same name

A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS., , , , , , , , and . ISSCC, page 110-111. IEEE, (2008)20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver., , , , , , , , , and 3 other author(s). ISCAS, page 1-5. IEEE, (2018)A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS., , , , , , , , , and . VLSI Circuits, page 53-54. IEEE, (2018)Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 51 (3): 636-648 (2016)A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS., , , , , and . J. Solid-State Circuits, 44 (11): 2901-2910 (2009)A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth., , , , , , , , and . J. Solid-State Circuits, 43 (12): 2905-2920 (2008)A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 55 (1): 38-48 (2020)A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS., , , , , , , , , and 2 other author(s). ESSCIRC, page 148-151. IEEE, (2015)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)