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Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution., , , , , , , , , and 28 other author(s). SC, page 27-38. IEEE, (2014)22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)Low-Power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers Operating at ≪ 5 mW/Gb/s/link., , , , , , , and . J. Solid-State Circuits, 44 (1): 301-313 (2009)Electrical Performance of the Recessed Probe Launch Technique for Measurement of Embedded Multilayer Structures., , , , , and . IEEE Trans. Instrumentation and Measurement, 61 (12): 3198-3206 (2012)A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 50 (12): 3120-3132 (2015)Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology., , , , , , , , , and 5 other author(s). CICC, page 659-662. IEEE, (2005)A ≪5mW/Gb/s/link, 16×10Gb/s Bi-Directional Single-Chip CMOS Optical Transceiver for Board-Level Optical Interconnects., , , , , , , and . ISSCC, page 294-295. IEEE, (2008)A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology., , , , , , , , , and 6 other author(s). CICC, page 1-4. IEEE, (2014)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 53 (4): 1227-1237 (2018)A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 52 (12): 3458-3473 (2017)