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Mismatch analysis and statistical design at 65 nm and below., , , , and . CICC, page 9-12. IEEE, (2008)An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection., , , and . CICC, page 1-4. IEEE, (2010)A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS., and . CICC, page 153-156. IEEE, (2008)Post-silicon calibration of analog CMOS using phase-change memory cells., , , , , , and . ESSCIRC, page 423-426. IEEE, (2011)Statistical modeling and post manufacturing configuration for scaled analog CMOS., , and . CICC, page 1-4. IEEE, (2010)A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS., , , , , , and . ISSCC, page 122-124. IEEE, (2019)22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS., , and . ISSCC, page 418-420. IEEE, (2012)Optical receivers using DFE-IIR equalization., , and . ISSCC, page 130-131. IEEE, (2013)Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"., , , , , , and . J. Solid-State Circuits, 55 (4): 1124 (2020)