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Errata Erratum to Ä 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"., , , , , , and . J. Solid-State Circuits, 55 (4): 1124 (2020)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 53 (4): 1227-1237 (2018)A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 52 (12): 3458-3473 (2017)A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 50 (12): 3120-3132 (2015)A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 53 (4): 1214-1226 (2018)A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS., , , , , , and . J. Solid-State Circuits, 55 (1): 19-26 (2020)Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs., , , and . J. Solid-State Circuits, 46 (8): 1904-1918 (2011)