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Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology.

, , , , , , , , , , , , , , and . CICC, page 659-662. IEEE, (2005)

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Three-dimensional silicon integration., , , , , , , , , and 6 other author(s). IBM Journal of Research and Development, 52 (6): 553-569 (2008)Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection., , , , , , , , , and 10 other author(s). IBM Journal of Research and Development, 49 (4-5): 725-754 (2005)Wafer-level 3D integration technology., , , , , , , , , and . IBM Journal of Research and Development, 52 (6): 583-597 (2008)3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections., , , , , , , , , and 3 other author(s). IBM Journal of Research and Development, 52 (6): 611-622 (2008)Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology., , , , , , , , , and 5 other author(s). CICC, page 659-662. IEEE, (2005)Fabrication and characterization of robust through-silicon vias for silicon-carrier applications., , , , , , and . IBM Journal of Research and Development, 52 (6): 571-581 (2008)3D chip stacking with C4 technology., , , , , , , , , and 4 other author(s). IBM Journal of Research and Development, 52 (6): 599-609 (2008)