PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Braendli, Matthias"

Author of the publication

copydeleteadd this publication to your clipboard
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration.

, , , , , , , , , and . VLSI Circuits, page 275-276. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Matthias Keinert

Concept of a Computerized Numerical Control Kernel for Execution on Multi-core Processors, , and . IEEE Advanced Motion Control, page 599-604. (April 2016)

Matthias Bachmann

Matthias Bachmann

Matthias Bachmann

Matthias Bachmann

 

Other publications of authors with the same name

A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS., , , , , , , , , and 2 other author(s). ESSCIRC, page 148-151. IEEE, (2015)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 53 (4): 1227-1237 (2018)A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 52 (12): 3458-3473 (2017)20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver., , , , , , , , , and 3 other author(s). ISCAS, page 1-5. IEEE, (2018)Multi-gigabit GCM-AES Architecture Optimized for FPGAs., , , and . CHES, volume 4727 of Lecture Notes in Computer Science, page 227-238. Springer, (2007)Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 51 (3): 636-648 (2016)A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 55 (1): 38-48 (2020)A 28Gb/s source-series terminated TX in 32nm CMOS SOI., , , , , , , and . ISSCC, page 334-336. IEEE, (2012)