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30 dB SNDR at Nyquist in 14-nm CMOS FinFET.

L. Kull, D. Luu, C. Menolfi, M. Brändli, P. Francese, T. Morf, M. Kossel, A. Cevrero, I. Özkaya, and T. Toifl. J. Solid-State Circuits, 53 (12): 3508-3516 (2018)

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Tien Duc Luu University of Stuttgart

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Design considerations for 50G+ backplane links.T. Toifl, M. Braendli, A. Cevrero, P. Francese, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, I. Özkaya and 1 other author(s). ESSCIRC, page 477-482. IEEE, (2016)A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS.H. Yueksel, M. Braendli, A. Burg, G. Cherubini, R. Cideciyan, P. Francese, S. Furrer, M. Kossel, L. Kull, D. Luu and 3 other author(s). ESSCIRC, page 309-312. IEEE, (2016)Design considerations for 50G+ backplane links.T. Toifl, M. Braendli, A. Cevrero, P. Francese, M. Kossel, L. Kull, D. Luu, C. Menolfi, T. Morf, I. Ozkaya and 1 other author(s). ESSCIRC, page 477-482. IEEE, (2016)A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET.L. Kull, D. Luu, C. Menolfi, M. Brändli, P. Francese, T. Morf, M. Kossel, A. Cevrero, I. Özkaya, and T. Toifl. J. Solid-State Circuits, 53 (12): 3508-3516 (2018)A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration.L. Kull, D. Luu, C. Menolfi, T. Morf, P. Francese, M. Braendli, M. Kossel, A. Cevrero, I. Özkaya, and T. Toifl. VLSI Circuits, page 275-276. IEEE, (2018)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver.G. Kim, L. Kull, D. Luu, M. Braendli, C. Menolfi, P. Francese, C. Aprile, T. Morf, M. Kossel, A. Cevrero and 3 other author(s). ISCAS, page 1-5. IEEE, (2018)A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS.T. Toifl, C. Menolfi, M. Brändli, A. Cevrero, P. Francese, M. Kossel, L. Kull, D. Luu, T. Morf, and I. Özkaya. VLSI Circuits, page 53-54. IEEE, (2018)A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.G. Kim, M. Kossel, A. Cevrero, I. Özkaya, A. Burg, T. Toifl, Y. Leblebici, L. Kull, D. Luu, M. Braendli and 5 other author(s). J. Solid-State Circuits, 55 (1): 38-48 (2020)23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path.P. Francese, M. Braendli, C. Menolfi, M. Kossel, T. Morf, L. Kull, A. Cevrero, H. Yueksel, I. Oezkaya, D. Luu and 1 other author(s). ISSCC, page 408-409. IEEE, (2016)Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders.H. Yueksel, M. Braendli, A. Burg, G. Cherubini, R. Cideciyan, P. Francese, S. Furrer, M. Kossel, L. Kull, D. Luu and 3 other author(s). IEEE Trans. on Circuits and Systems, 65-I (10): 3529-3542 (2018)

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A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET.

Please choose a person to relate this publication to

Tien Duc Luu University of Stuttgart

Other publications of authors with the same name

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PUMA

Disambiguation of "Luu, Danny"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET.

Please choose a person to relate this publication to

Tien Duc Luu University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
DOI
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APA
Chicago
DIN 1505
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MSOffice XML

A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET.