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Disambiguation of "Kaul, Himanshu"

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A robust alternate repeater technique for high performance busses in the multi-core era.

, , , , and . ISCAS, page 372-375. IEEE, (2008)

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Prof. Dr. Giselher Kaule University of Stuttgart

 

Other publications of authors with the same name

High-Performance On-Chip Interconnect Circuit Technologies for sub-65nm CMOS.. SoCC, page 324. IEEE, (2005)Power-aware global signaling strategies., , , , , and . ISCAS (1), page 604-607. IEEE, (2005)DVS for On-Chip Bus Designs Based on Timing Error Correction, , , , and . CoRR, (2007)Active shielding of RLC global interconnects., , and . Timing Issues in the Specification and Synthesis of Digital Systems, page 98-104. ACM, (2002)DVS for On-Chip Bus Designs Based on Timing Error Correction., , , , and . DATE, page 80-85. IEEE Computer Society, (2005)A novel buffer circuit for energy efficient signaling in dual-VDD systems., and . ACM Great Lakes Symposium on VLSI, page 462-467. ACM, (2005)Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses., , , and . ISLPED, page 194-199. ACM, (2004)Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS., , , , , , , and . A-SSCC, page 1-4. IEEE, (2018)A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)