PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Anders, Mark"

Author of the publication

copydeleteadd this publication to your clipboard
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses.

, , , and . ISLPED, page 194-199. ACM, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Mark Burkhardt University of Stuttgart

Dr. Mark Hamilton University of Stuttgart

Mark Kurcsics University of Stuttgart

Dr. rer. nat. habil. Frederik Marks University of Stuttgart

Ph. D. Mark Ringenberg University of Stuttgart

 

Other publications of authors with the same name

Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS., , , , , , , and . A-SSCC, page 1-4. IEEE, (2018)Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses., , , and . ISLPED, page 194-199. ACM, (2004)A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2019)A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects., , , , and . SoCC, page 289-292. IEEE, (2006)A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS., , , , , , , , , and . A-SSCC, page 263-266. IEEE, (2018)A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS., , , , and . SoCC, page 25-28. IEEE, (2007)A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS., , , , , , , , , and 2 other author(s). CICC, page 1-4. IEEE, (2019)A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS., , , , , , , , , and . A-SSCC, page 253-256. IEEE, (2016)Negative bias instability in 4H-SiC MOSFETS: Evidence for structural changes in the SiC., , and . IRPS, page 3. IEEE, (2015)A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 55 (4): 945-955 (2020)