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Disambiguation of "Krishnamurthy, Ram"

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A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.

, , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)

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Astrid Yuliana Ramírez Hernández University of Stuttgart

Roman Ramminger University of Stuttgart

Johannes Ramme University of Stuttgart

Dr. Ulrike Ramming University of Stuttgart

Andrea Cristina Ramirez Herrera University of Stuttgart

 

Other publications of authors with the same name

A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects., , , , and . SoCC, page 289-292. IEEE, (2006)Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies., , and . Microelectronics Journal, 36 (9): 801-809 (2005)Self Calibrating Circuit Design for Variation Tolerant VLSI Systems., , , , and . IOLTS, page 100-105. IEEE Computer Society, (2005)A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS., , , , , , , , , and . A-SSCC, page 263-266. IEEE, (2018)A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores., , , , and . VLSI Design, page 273-278. IEEE Computer Society, (2008)High-performance energy-efficient memory circuit technologies for sub-45nm technologies., and . SoCC, page 322. IEEE, (2006)Comparison of high-performance VLSI adders in the energy-delay space., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (6): 754-758 (2005)Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (11): 1225-1238 (2005)A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core., , , , , , , , and . ISSCC, page 353-365. IEEE, (2006)A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS., , , , , , , and . ISSCC, page 110-111. IEEE, (2010)