Author of the publication

Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.

G. Chen, M. Anders, H. Kaul, S. Satpathy, S. Mathew, S. Hsu, A. Agarwal, R. Krishnamurthy, V. De, and S. Borkar. IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

K. Stahl

K. Gaiser

Hong Chen University of Stuttgart

Tzu-Ying Chen University of Stuttgart

Replication Data for: Structural development of a novel punctually supported timber building system for multi-storey construction : Experimental Data: Tension Tests of the Edge ConnectionA. Krtschil, L. Orozco, A. Shah, T. Chen, A. Menges, and J. Knippers. Dataset, (2024)Related to: Anna Krtschil, Luis Orozco, Simon Bechert, Hans Jakob Wagner, Felix Amtsberg, Tzu-Ying Chen, Anand Shah, Achim Menges, Jan Knippers, "Structural development of a novel punctually supported timber building system for multi-storey construction", Journal of Building Engineering, Volume 58, 2022, pages 104972. doi: 10.1016/j.jobe.2022.104972.

K. Lindow

Other publications of authors with the same name

A dense 45nm half-differential SRAM with lower minimum operating voltage.G. Chen, M. Wieckowski, D. Kim, D. Blaauw, and D. Sylvester. ISCAS, page 57-60. IEEE, (2011)Circuit design advances to enable ubiquitous sensing environments.M. Seok, S. Hanson, M. Wieckowski, G. Chen, Y. Lin, D. Blaauw, and D. Sylvester. ISCAS, page 285-288. IEEE, (2010)A highly resilient routing algorithm for fault-tolerant NoCs.D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester, and D. Blaauw. DATE, page 21-26. IEEE, (2009)Analysis and measurement of the stability of dual-resonator oscillators.H. Ghaed, G. Chen, D. Blaauw, and D. Sylvester. RWS, page 219-222. IEEE, (2012)A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS.G. Chen, R. Kumar, H. Sumbul, P. Knag, and R. Krishnamurthy. VLSI Circuits, page 255-256. IEEE, (2018)A Reliable Routing Architecture and Algorithm for NoCs.A. DeOrio, D. Fick, V. Bertacco, D. Sylvester, D. Blaauw, J. Hu, and G. Chen. IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (5): 726-739 (2012)µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS.S. Mathew, D. Johnston, S. Satpathy, V. Suresh, P. Newman, M. Anders, H. Kaul, A. Agarwal, S. Hsu, G. Chen and 1 other author(s). IEEE J. Solid State Circuits, 51 (7): 1695-1704 (2016)A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications.M. Kar, A. Agarwal, S. Hsu, D. Moloney, G. Chen, R. Kumar, H. Sumbul, P. Knag, M. Anders, H. Kaul and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs.E. Nurvitadhi, D. Kwon, A. Jafari, A. Boutros, J. Sim, P. Tomson, H. Sumbul, G. Chen, P. Knag, R. Kumar and 6 other author(s). FCCM, page 199-207. IEEE, (2019)250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS.S. Satpathy, S. Mathew, V. Suresh, M. Anders, H. Kaul, A. Agarwal, S. Hsu, G. Chen, and R. Krishnamurthy. VLSI Circuits, page 1-2. IEEE, (2016)

PUMA

Disambiguation of "Chen, Gregory K."

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.

Please choose a person to relate this publication to

K. Stahl

K. Gaiser

Hong Chen University of Stuttgart

Tzu-Ying Chen University of Stuttgart

K. Lindow

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Chen, Gregory K."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.

Please choose a person to relate this publication to

K. Stahl

K. Gaiser

Hong Chen University of Stuttgart

Tzu-Ying Chen University of Stuttgart

K. Lindow

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.