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A robust alternate repeater technique for high performance busses in the multi-core era.

, , , , and . ISCAS, page 372-375. IEEE, (2008)

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Extended dynamic voltage scaling for low power design., , , and . SoCC, page 389-394. IEEE, (2004)Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis., , , , and . VLSI Design, page 77-. IEEE Computer Society, (2002)Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization., , , , and . ISQED, page 88-93. IEEE Computer Society, (2005)Power Gating with Multiple Sleep Modes., , , and . ISQED, page 633-637. IEEE Computer Society, (2006)Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices., , and . ISQED, page 158-162. IEEE, (2010)An Energy Efficient Parallel Architecture Using Near Threshold Operation., , , , and . PACT, page 175-188. IEEE Computer Society, (2007)XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems., , , , , , , , and . PACT, page 75-86. ACM, (2012)Victim Alignment in Crosstalk-Aware Timing Analysis., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (2): 261-274 (2010)High performance level conversion for dual VDD design., and . IEEE Trans. VLSI Syst., 12 (9): 926-936 (2004)Improved a priori interconnect predictions and technology extrapolation in the GTX system., , , , , , , and . IEEE Trans. VLSI Syst., 11 (1): 3-14 (2003)