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A robust alternate repeater technique for high performance busses in the multi-core era.

, , , , and . ISCAS, page 372-375. IEEE, (2008)

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Dynamic and leakage power reduction of ASICs using configurable threshold logic gates., , , , and . CICC, page 1-4. IEEE, (2015)Guest Editors' Introduction: Frontiers of Hardware and Algorithms for On-chip Learning., , , and . JETC, 14 (2): 14:1-14:2 (2018)Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs., , , , , and . CoRR, (2016)Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (1): 1-5 (2018)Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks., , , , , and . ICASSP, page 1393-1397. IEEE, (2019)Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning., , , , , , , , , and . BioCAS, page 536-539. IEEE, (2014)Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing., , , and . ICCAD, page 15. ACM, (2016)Self-Time Regenerators for High-Speed and Low-Power Interconnect., , , and . ISQED, page 621-626. IEEE Computer Society, (2007)Low Power and Trusted Machine Learning., , , , and . ACM Great Lakes Symposium on VLSI, page 515. ACM, (2018)Designing ECG-based physical unclonable function for security of wearable devices., , , and . EMBC, page 3509-3512. IEEE, (2017)