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Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms.

, , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (1): 1-5 (2018)

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A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme., , , , , , , , , and . J. Solid-State Circuits, 46 (4): 815-827 (2011)Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements., , , , , and . J. Solid-State Circuits, 45 (10): 2142-2155 (2010)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_TH$ Read-Port, and Offset Cell VDD Biasing Techniques., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (10): 2558-2569 (2013)17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)SRAM Cell Current in Low Leakage Design., , , , , , , , , and 1 other author(s). MTDT, page 65-70. IEEE Computer Society, (2006)Crosstalk-insensitive via-programming ROMs using content-aware design framework., , and . IEEE Trans. on Circuits and Systems, 53-II (6): 443-447 (2006)Wide VDD Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems., , and . IEEE Trans. on Circuits and Systems, 56-I (8): 1657-1667 (2009)A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques., , , , , , , , , and 2 other author(s). VLSIC, page 112-113. IEEE, (2012)A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing., , , , , , , , , and . J. Solid-State Circuits, 51 (11): 2786-2798 (2016)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 52 (10): 2769-2785 (2017)