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A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_TH$ Read-Port, and Offset Cell VDD Biasing Techniques.

M. Chang, M. Chen, L. Chen, S. Yang, Y. Kuo, J. Wu, H. Su, Y. Chu, W. Wu, T. Yang, und H. Yamauchi. J. Solid-State Circuits, 48 (10): 2558-2569 (2013)

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Hanchuan Wu University of Stuttgart

Jen Sikos

Yongxiang Wu University of Stuttgart

Sabrina Jenne University of Stuttgart

Marcus Jenke

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