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A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.

J. Wu, Y. Chen, M. Chang, P. Chou, C. Chen, H. Liao, M. Chen, Y. Chu, W. Wu, and H. Yamauchi. J. Solid-State Circuits, 46 (4): 815-827 (2011)

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Anh Chu University of Stuttgart

Xu Chu

Dr. -Ing. Xu Chu University of Stuttgart

Yiwen Yuan University of Stuttgart

Dr. rer. nat. Shiang-Yu Huang University of Stuttgart

Other publications of authors with the same name

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.T. Lin, C. Chien, P. Chang, C. Chen, P. Wang, T. Shyu, C. Chou, S. Luo, J. Guo, T. Chen and 8 other author(s). ISSCC, page 158-159. IEEE, (2013)Energy-efficient RISC design with on-demand circuit-level timing speculation.T. Lin, Y. Kuo, Y. Tsai, T. Shyu, and Y. Chu. ASP-DAC, page 477-478. IEEE, (2012)An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation.M. Chen, M. Chang, Y. Chu, and W. Hwang. SoCC, page 5-10. IEEE, (2012)Design of STR level converters for SoCs using the multi-island dual-VDD design technique.J. Wang, Y. Chang, C. Yeh, and Y. Chu. ISCAS, IEEE, (2006)A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS.C. Cheng, J. Wang, P. Chou, S. Chen, C. Sun, Y. Chu, and T. Yang. A-SSCC, page 361-364. IEEE, (2014)Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.S. Luo, K. Chang, M. Chen, C. Huang, Y. Chiu, P. Chen, L. Cheng, C. Liu, and Y. Chu. IEEE Trans. on Circuits and Systems, 61-II (12): 947-951 (2014)Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.H. Huang, J. Wang, Y. Chu, T. Wu, K. Cheng, and C. Wu. ISCAS, page 1572-1575. IEEE, (1995)PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems.P. Wu, Y. Kuo, C. Wu, C. Chuang, Y. Chu, and W. Hwang. SoCC, page 136-139. IEEE, (2014)Collaborative voltage scaling with online STA and variable-latency datapath.T. Lin, P. Hsiao, C. Lin, S. Kuo, C. Lin, Y. Kuo, C. Liu, and Y. Chu. ACM Great Lakes Symposium on VLSI, page 347-352. ACM, (2010)An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications.C. Wu, K. Lin, Y. Kuo, P. Chen, Y. Chu, and W. Hwang. ISCAS, page 1370-1373. IEEE, (2015)

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Disambiguation of "Chu, Yuan-Hua"

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A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.

Please choose a person to relate this publication to

Anh Chu University of Stuttgart

Xu Chu

Dr. -Ing. Xu Chu University of Stuttgart

Yiwen Yuan University of Stuttgart

Dr. rer. nat. Shiang-Yu Huang University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Chu, Yuan-Hua"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.

Please choose a person to relate this publication to

Anh Chu University of Stuttgart

Xu Chu

Dr. -Ing. Xu Chu University of Stuttgart

Yiwen Yuan University of Stuttgart

Dr. rer. nat. Shiang-Yu Huang University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.