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Disambiguation of "Yamauchi, Hiroyuki"

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A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.

, , , , , , , , , and . J. Solid-State Circuits, 46 (4): 815-827 (2011)

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Other publications of authors with the same name

A discussion on SRAM forward/inverse problem analyses for RTN long-tail distributions., , and . ISVLSI, page 58-63. IEEE Computer Socity, (2013)A Phase Shifting Multiple Filter Design Methodology for Lucy-Richardson Deconvolution of Log-Mixtures Complex RTN Tail Distribution., and . SBCCI, page 20:1-20:6. ACM, (2015)Incorporating Fuzzy Set Theory and Matrix Logic in Multi-Layer Logic - A Preliminary Consideration., and . RSFDGrC, volume 1711 of Lecture Notes in Computer Science, page 304-313. Springer, (1999)Processing Of Syntax And Semantics Of Natural Language By Predicate Logic Of Predicate Logic.. COLING, page 389-396. (1980)A 45nm dual-port SRAM with write and read capability enhancement at low voltage., , , , , , , , and . SoCC, page 211-214. IEEE, (2007)A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme., , , , , , , , , and . J. Solid-State Circuits, 46 (4): 815-827 (2011)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_TH$ Read-Port, and Offset Cell VDD Biasing Techniques., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (10): 2558-2569 (2013)A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques., , , , , , , , , and 2 other author(s). VLSIC, page 112-113. IEEE, (2012)A filter design for blind deconvolution to decouple unknown RDF/RTN factors from complexly coupled SRAM margin variations., and . LASCAS, page 247-250. IEEE, (2016)A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors., , , , , , , , , and . IEEE Trans. on Circuits and Systems, 66-I (11): 4172-4185 (2019)