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A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.

, , , , , , , , , and . IEEE Trans. on Circuits and Systems, 66-I (11): 4172-4185 (2019)

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A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection., , , , , and . IEEE J. Solid State Circuits, 57 (1): 68-79 (2022)A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS., , , , , , , , , and 3 other author(s). VLSI Circuits, page 120-. IEEE, (2019)7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications., , , , , , , , , and 3 other author(s). ISSCC, page 134-135. IEEE, (2016)Parallelizing SRAM arrays with customized bit-cell for binary neural networks., , , , , , , , and . DAC, page 21:1-21:6. ACM, (2018)A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors., , , , , , , , , and . IEEE Trans. on Circuits and Systems, 66-I (11): 4172-4185 (2019)A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors., , , , , , , , , and 1 other author(s). ISSCC, page 496-498. IEEE, (2018)A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 52 (1): 218-228 (2017)