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7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications.

, , , , , , , , , , , , and . ISSCC, page 134-135. IEEE, (2016)

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Opportunities for Analog Coding in Emerging Memory Systems., , , , , , , and . CoRR, (2017)Experimental Demonstration of Array-level Learning with Phase Change Synaptic Devices., , , , , , and . CoRR, (2014)Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses., , , , , , , , and . CoRR, (2016)7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications., , , , , , , , , and 3 other author(s). ISSCC, page 134-135. IEEE, (2016)Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array., , , , , , and . CoRR, (2014)Recent Progress in Phase-Change Memory Technology., , , , , , , , , and 2 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (2): 146-162 (2016)Reliability Challenges with Materials for Analog Computing., , , , , , , , , and 8 other author(s). IRPS, page 1-10. IEEE, (2019)A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 52 (1): 218-228 (2017)