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A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.

, , , , , , , , , and . IEEE Trans. on Circuits and Systems, 66-I (11): 4172-4185 (2019)

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17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)SRAM Cell Current in Low Leakage Design., , , , , , , , , and 1 other author(s). MTDT, page 65-70. IEEE Computer Society, (2006)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 52 (10): 2769-2785 (2017)A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors., , , , , , , , , and 12 other author(s). ISSCC, page 388-390. IEEE, (2019)Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices., , , , , , , , , and 3 other author(s). VLSI Circuits, page 166-. IEEE, (2019)Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory., , , , , , , , , and 47 other author(s). IEEE Trans. VLSI Syst., 27 (2): 253-280 (2019)A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM., , , , and . IEEE Access, (2018)Wide VDD Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems., , and . IEEE Trans. on Circuits and Systems, 56-I (8): 1657-1667 (2009)Crosstalk-insensitive via-programming ROMs using content-aware design framework., , and . IEEE Trans. on Circuits and Systems, 53-II (6): 443-447 (2006)A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme., , , , , , , , , and . J. Solid-State Circuits, 46 (4): 815-827 (2011)