A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.
@article{journals/jssc/WangLLSLYLLCCLK17,
added-at = {2018-11-02T00:00:00.000+0100},
author = {Wang, Zhibo and Liu, Yongpan and Lee, Albert and Su, Fang and Lo, Chieh-Pu and Yuan, Zhe and Li, Jinyang and Lin, Chien-Chen and Chen, Wei-Hao and Chiu, Hsiao-Yun and Lin, Wei-En and King, Ya-Chin and Lin, Chrong Jung and Amiri, Pedram Khalili and Wang, Kang-Lung and Chang, Meng-Fan and Yang, Huazhong},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2b3a399e508eb5b1f5eb6f76186c5483f/dblp},
ee = {https://doi.org/10.1109/JSSC.2017.2724024},
interhash = {e41c1c53834676a07317a1cfd8c145a2},
intrahash = {b3a399e508eb5b1f5eb6f76186c5483f},
journal = {J. Solid-State Circuits},
keywords = {dblp},
number = 10,
pages = {2769-2785},
timestamp = {2019-09-27T06:09:16.000+0200},
title = {A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc52.html#WangLLSLYLLCCLK17},
volume = 52,
year = 2017
}