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Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks.

G. Srivastava, D. Kadetotad, S. Yin, V. Berisha, C. Chakrabarti, and J. sun Seo. ICASSP, page 1393-1397. IEEE, (2019)

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Deepak Deepak University of Stuttgart

Ganesh Deepak Rupakula University of Stuttgart

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Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.D. Kadetotad, Z. Xu, A. Mohanty, P. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, and J. sun Seo. IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (2): 194-204 (2015)Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications.D. Kadetotad, S. Arunachalam, C. Chakrabarti, and J. sun Seo. ICCAD, page 78. ACM, (2016)Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs.R. Tapiador-Morales, A. Rios-Navarro, A. Linares-Barranco, M. Kim, D. Kadetotad, and J. sun Seo. IWANN (2), volume 10306 of Lecture Notes in Computer Science, page 271-282. Springer, (2017)Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.P. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J. sun Seo, Y. Cao, and S. Yu. DATE, page 854-859. ACM, (2015)A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS.M. Kim, A. Mohanty, D. Kadetotad, L. Wei, X. He, Y. Cao, and J. sun Seo. IEEE Trans. on Circuits and Systems, 66-I (10): 3843-3853 (2019)A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip.D. Kadetotad, V. Berisha, C. Chakrabarti, and J. Seo. ESSCIRC, page 119-122. IEEE, (2019)A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.M. Kim, A. Mohanty, D. Kadetotad, N. Suda, L. Wei, P. Saseendran, X. He, Y. Cao, and J. sun Seo. ISCAS, page 1-4. IEEE, (2017)ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression.S. Cherupally, G. Srivastava, S. Yin, D. Kadetotad, C. Bae, S. Kim, and J. sun Seo. ISCAS, page 1-5. IEEE, (2019)A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring.S. Yin, M. Kim, D. Kadetotad, Y. Liu, C. Bae, S. Kim, Y. Cao, and J. sun Seo. J. Solid-State Circuits, 54 (8): 2316-2326 (2019)Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs.R. Tapiador, A. Rios-Navarro, A. Linares-Barranco, M. Kim, D. Kadetotad, and J. sun Seo. CoRR, (2016)

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Disambiguation of "Kadetotad, Deepak"

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Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks.

Please choose a person to relate this publication to

Deepak Deepak University of Stuttgart

Ganesh Deepak Rupakula University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Kadetotad, Deepak"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks.

Please choose a person to relate this publication to

Deepak Deepak University of Stuttgart

Ganesh Deepak Rupakula University of Stuttgart

Other publications of authors with the same name

Disambiguation

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Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks.