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Disambiguation of "sun Seo, Jae"

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Dynamic and leakage power reduction of ASICs using configurable threshold logic gates.

, , , , and . CICC, page 1-4. IEEE, (2015)

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Florian Jaensch University of Stuttgart

Dr. Kaicong Sun University of Stuttgart

Jun. -Prof. Sun Hea Hong University of Stuttgart

 

Other publications of authors with the same name

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA., , , and . IEEE Trans. VLSI Syst., 26 (7): 1354-1367 (2018)A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware., , , , , , , and . Signal Processing Systems, 90 (5): 727-741 (2018)Process Scalability of Pulse-Based Circuits for Analog Image Convolution., , , , , , , , , and 3 other author(s). IEEE Trans. on Circuits and Systems, 65-I (9): 2929-2938 (2018)A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks., , , , and . SiPS, page 13-18. IEEE, (2018)Bi-Level Rare Temporal Pattern Detection., , , and . ICDM, page 719-728. IEEE Computer Society, (2016)XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks., , , , , and . DATE, page 1423-1428. IEEE, (2018)Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks., , , , and . VLSI-DAT, page 1-2. IEEE, (2019)XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism., , , and . ACM Great Lakes Symposium on VLSI, page 417-422. ACM, (2019)In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter., , , , , , and . ISSCC, page 188-189. IEEE, (2010)A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS., , , , , , and . IEEE Trans. on Circuits and Systems, 66-I (10): 3843-3853 (2019)