%0 Conference Paper %1 conf/glvlsi/JiangYSS19 %A Jiang, Zhewei %A Yin, Shihui %A sun Seo, Jae %A Seok, Mingoo %B ACM Great Lakes Symposium on VLSI %D 2019 %E Homayoun, Houman %E Taskin, Baris %E Mohsenin, Tinoosh %E Zhao, Weisheng %I ACM %K dblp %P 417-422 %T XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2019.html#JiangYSS19 %@ 978-1-4503-6252-8

@inproceedings{conf/glvlsi/JiangYSS19, added-at = {2019-05-16T00:00:00.000+0200}, author = {Jiang, Zhewei and Yin, Shihui and sun Seo, Jae and Seok, Mingoo}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/249267dd0ca3c58124d4453bb1c51b422/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2019}, editor = {Homayoun, Houman and Taskin, Baris and Mohsenin, Tinoosh and Zhao, Weisheng}, ee = {https://doi.org/10.1145/3299874.3319458}, interhash = {b9b7742c2eeec0a17dbe6a92aca1a980}, intrahash = {49267dd0ca3c58124d4453bb1c51b422}, isbn = {978-1-4503-6252-8}, keywords = {dblp}, pages = {417-422}, publisher = {ACM}, timestamp = {2019-09-27T17:13:07.000+0200}, title = {XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2019.html#JiangYSS19}, year = 2019 }