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Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.

D. Kadetotad, Z. Xu, A. Mohanty, P. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, and J. sun Seo. BioCAS, page 536-539. IEEE, (2014)

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Sarthak Mohanty University of Stuttgart

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Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip.P. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J. sun Seo, Y. Cao, and S. Yu. DATE, page 854-859. ACM, (2015)Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches.X. Du, G. Krishnan, A. Mohanty, Z. Li, G. Charan, and Y. Cao. CoRR, (2019)Duty cycle shift under static/dynamic aging in 28nm HK-MG technology.K. Sutaria, P. Ren, A. Mohanty, X. Feng, R. Wang, R. Huang, and Y. Cao. IRPS, page 7. IEEE, (2015)A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS.M. Kim, A. Mohanty, D. Kadetotad, L. Wei, X. He, Y. Cao, and J. sun Seo. IEEE Trans. on Circuits and Systems, 66-I (10): 3843-3853 (2019)RTN in Scaled Transistors for On-Chip Random Seed Generation.A. Mohanty, K. Sutaria, H. Awano, T. Sato, and Y. Cao. IEEE Trans. VLSI Syst., 25 (8): 2248-2257 (2017)Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration.D. Kadetotad, Z. Xu, A. Mohanty, P. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, and J. sun Seo. IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (2): 194-204 (2015)Algorithm and Hardware Design for Efficient Deep Learning Inference.A. Mohanty. Arizona State University, Tempe, USA, (2018)base-search.net (ftarizonastateun:item:51790).Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks.N. Suda, V. Chandra, G. Dasika, A. Mohanty, Y. Ma, S. Vrudhula, J. sun Seo, and Y. Cao. FPGA, page 16-25. ACM, (2016)Towards a Wearable Cough Detector Based on Neural Networks.P. Kadambi, A. Mohanty, H. Ren, J. Smith, K. McGuinnes, K. Holt, A. Furtwaengler, R. Slepetys, Z. Yang, J. sun Seo and 3 other author(s). ICASSP, page 2161-2165. IEEE, (2018)A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.M. Kim, A. Mohanty, D. Kadetotad, N. Suda, L. Wei, P. Saseendran, X. He, Y. Cao, and J. sun Seo. ISCAS, page 1-4. IEEE, (2017)

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Disambiguation of "Mohanty, Abinash"

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Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.

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Sarthak Mohanty University of Stuttgart

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.

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Sarthak Mohanty University of Stuttgart

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Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning.