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An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms.

S. Satpathy, S. Mathew, V. Suresh, M. Anders, H. Kaul, A. Agarwal, S. Hsu, R. Krishnamurthy, and V. De. VLSI Circuits, page 169-170. IEEE, (2018)

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Steven Minden University of Stuttgart

Steven Presser University of Stuttgart

Steven Jöns University of Stuttgart

Steven Scharr University of Stuttgart

Steven Biele University of Stuttgart

Other publications of authors with the same name

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies.B. Chatterjee, M. Sachdev, S. Hsu, R. Krishnamurthy, and S. Borkar. ISLPED, page 122-127. ACM, (2003)Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS.H. Kaul, M. Anders, S. Mathew, V. Suresh, S. Satpathy, A. Agarwal, S. Hsu, and R. Krishnamurthy. A-SSCC, page 1-4. IEEE, (2018)A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.G. Chen, M. Anders, H. Kaul, S. Satpathy, S. Mathew, S. Hsu, A. Agarwal, R. Krishnamurthy, V. De, and S. Borkar. IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS.S. Satpathy, S. Mathew, V. Suresh, M. Anders, H. Kaul, A. Agarwal, S. Hsu, G. Chen, R. Krishnamurthy, and V. De. IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities.S. Vangal, S. Paul, S. Hsu, A. Agarwal, S. Kumar, R. Krishnamurthy, H. Krishnamurthy, J. Tschanz, V. De, and C. Kim. IEEE Trans. Very Large Scale Integr. Syst., 29 (5): 843-856 (2021)34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms.S. Satpathy, S. Mathew, V. Suresh, V. Gopal, J. Guilford, M. Anders, H. Kaul, A. Agarwal, S. Hsu, and K. Krisnnamurthy. ESSCIRC, page 90-93. IEEE, (2018)A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS.H. Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, F. Sheikh, R. Krishnamurthy, and S. Borkar. ISSCC, page 182-184. IEEE, (2012)25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS.A. Agarwal, S. Hsu, S. Realov, M. Anders, G. Chen, M. Kar, R. Kumar, H. Sumbul, P. Knag, H. Kaul and 4 other author(s). ISSCC, page 392-394. IEEE, (2020)A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS.M. Anders, S. Mathew, S. Hsu, R. Krishnamurthy, and S. Borkar. ISSCC, page 256-600. IEEE, (2007)A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.R. Kumar, V. Suresh, M. Kar, S. Satpathy, M. Anders, H. Kaul, A. Agarwal, S. Hsu, G. Chen, R. Krishnamurthy and 2 other author(s). VLSI Circuits, page 234-. IEEE, (2019)

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Disambiguation of "Hsu, Steven"