%0 Conference Paper %1 conf/vlsic/KumarSKSAKAHCKD19 %A Kumar, Raghavan %A Suresh, Vikram B. %A Kar, Monodeep %A Satpathy, Sudhir %A Anders, Mark A. %A Kaul, Himanshu %A Agarwal, Amit %A Hsu, Steven %A Chen, Gregory K. %A Krishnamurthy, Ram %A De, Vivek %A Mathew, Sanu %B VLSI Circuits %D 2019 %I IEEE %K dblp %P 234- %T A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#KumarSKSAKAHCKD19 %@ 978-4-86348-720-8

@inproceedings{conf/vlsic/KumarSKSAKAHCKD19, added-at = {2022-02-25T00:00:00.000+0100}, author = {Kumar, Raghavan and Suresh, Vikram B. and Kar, Monodeep and Satpathy, Sudhir and Anders, Mark A. and Kaul, Himanshu and Agarwal, Amit and Hsu, Steven and Chen, Gregory K. and Krishnamurthy, Ram and De, Vivek and Mathew, Sanu}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2ab21cf62bea28493fc515a08e66551a2/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2019}, ee = {https://doi.org/10.23919/VLSIC.2019.8778041}, interhash = {ca9d88b3314160e74ee6a589269e7a8b}, intrahash = {ab21cf62bea28493fc515a08e66551a2}, isbn = {978-4-86348-720-8}, keywords = {dblp}, pages = {234-}, publisher = {IEEE}, timestamp = {2022-03-01T07:24:28.000+0100}, title = {A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#KumarSKSAKAHCKD19}, year = 2019 }