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Disambiguation of "Kumar, Saurabh"

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Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities.

, , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (5): 843-856 (2021)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Manish Kumar University of Stuttgart

Shreya Kumar University of Stuttgart

Tarun Kumar Mitruka Vinod Kumar Mitruka University of Stuttgart

Ratnesh Kumar Gupta University of Stuttgart

Bhupender Kumar Saini University of Stuttgart

 

Other publications of authors with the same name

A Simple and Efficient Antenna Subset Selection Scheme for MIMO Systems., and . ICASSP (4), page 805-808. IEEE, (2006)State Space Decomposition and Subgoal Creation for Transfer in Deep Reinforcement Learning., , , , and . CoRR, (2017)Software Engineering: A System Dynamics Simulated Pedagogical Practice., and . CSEE&T, page 280-283. IEEE Computer Society, (2009)Online Sensor Hallucination via Knowledge Distillation for Multimodal Image Classification., , and . CoRR, (2019)Modelling Of Mist Reactor: Effect Of Packing Fraction And Film Thickness On The Growth Of Hairy Roots., and . ECMS, page 117-123. European Council for Modeling and Simulation, (2013)Onboard Hyperspectral Image Compression Using Compressed Sensing and Deep Learning., , , and . ECCV Workshops (2), volume 11130 of Lecture Notes in Computer Science, page 30-42. Springer, (2018)DeepMDP: Learning Continuous Latent Space Models for Representation Learning., , , , and . ICML, volume 97 of Proceedings of Machine Learning Research, page 2170-2179. PMLR, (2019)Statistics and Samples in Distributional Reinforcement Learning., , , , , and . ICML, volume 97 of Proceedings of Machine Learning Research, page 5528-5536. PMLR, (2019)A Real-Time IVR Platform for Community Radio., , , , , , , , , and 9 other author(s). CHI, page 343-354. ACM, (2016)Iterative and Fully Pipelined High Throughput Efficient Architectures of AES in FPGA and ASIC., , and . Journal of Circuits, Systems, and Computers, 25 (5): 1650049:1-1650049:29 (2016)