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CMOS VT characterization by capacitance measurements in FDSOI PIN gated diodes.

C. Navarro, M. Bawedin, F. Andrieu, J. Cluzel, X. Garros, and S. Cristoloveanu. ESSDERC, page 405-408. IEEE, (2014)

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Hot-Carrier Reliability for Si and SiGe HBTs: Aging Procedure, Extrapolation Model Limitations and Applications.N. Revil, and X. Garros. Microelectronics Reliability, 41 (9-10): 1307-1312 (2001)Process dependence of BTI reliability in advanced HK MG stacks.X. Garros, M. Casse, M. Rafik, C. Fenouillet-Béranger, G. Reimbold, F. Martin, C. Wiemer, and F. Boulanger. Microelectronics Reliability, 49 (9-11): 982-988 (2009)CMOS VT characterization by capacitance measurements in FDSOI PIN gated diodes.C. Navarro, M. Bawedin, F. Andrieu, J. Cluzel, X. Garros, and S. Cristoloveanu. ESSDERC, page 405-408. IEEE, (2014)Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices.J. Micout, Q. Rafhay, X. Garros, M. Casse, J. Coignus, L. Pasini, C. Lu, N. Rambal, C. Fenouillet-Béranger, L. Brunet and 5 other author(s). ESSDERC, page 144-147. IEEE, (2017)Impact of Passive & Active Load Gate Impedance on Breakdown Hardness in 28nm FDSOI Technology.A. Nguyen, X. Garros, M. Rafik, F. Cacho, D. Roy, X. Federspiel, and F. Gaillard. IRPS, page 1-5. IEEE, (2019)Performance & reliability of 3D architectures (πfet, Finfet, Ωfet).A. Laurent, X. Garros, S. Barraud, J. Pelloux-Prayer, M. Casse, F. Gaillard, X. Federspiel, D. Roy, E. Vincent, and G. Ghibaudo. IRPS, page 6. IEEE, (2018)Performance and reliability of strained SOI transistors for advanced planar FDSOI technology.G. Besnard, X. Garros, A. Subirats, F. Andrieu, X. Federspiel, M. Rafik, W. Schwarzenbach, G. Reimbold, O. Faynot, and S. Cristoloveanu. IRPS, page 2. IEEE, (2015)Noise-induced dynamic variability in nano-scale CMOS SRAM cells.C. Theodorou, M. Fadlallah, X. Garros, C. Dimitriadis, and G. Ghibaudo. ESSDERC, page 256-259. IEEE, (2016)AC TDDB extensive study for an enlargement of its impact and benefit on circuit lifetime assessment.M. Rafik, A. Nguyen, X. Garros, M. Arabi, X. Federspiel, and C. Diouf. IRPS, page 4. IEEE, (2018)A novel insight of pBTI degradation in GaN-on-Si E-mode MOSc-HEMT.W. Vandendaele, X. Garros, T. Lorin, E. Morvan, A. Torres, R. Escoffier, M. Jaud, M. Plissonnier, and F. Gaillard. IRPS, page 4. IEEE, (2018)

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CMOS VT characterization by capacitance measurements in FDSOI PIN gated diodes.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML CMOS VT characterization by capacitance measurements in FDSOI PIN gated diodes.

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CMOS VT characterization by capacitance measurements in FDSOI PIN gated diodes.