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Disambiguation of "Barraud, Sylvain"

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Performance & reliability of 3D architectures (πfet, Finfet, Ωfet).

, , , , , , , , , and . IRPS, page 6. IEEE, (2018)

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Performance & reliability of 3D architectures (πfet, Finfet, Ωfet)., , , , , , , , , and . IRPS, page 6. IEEE, (2018)Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model., , , , , , , and . ESSDERC, page 210-213. IEEE, (2015)Statistical characterization of drain current local and global variability in sub 15nm Si/SiGe Trigate pMOSFETs., , , , , and . ESSDERC, page 142-145. IEEE, (2016)Drain current model for short-channel triple gate junctionless nanowire transistors., , , , , , , and . Microelectronics Reliability, (2016)Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities., , , , , , , , , and 6 other author(s). ESSDERC, page 121-124. IEEE, (2012)Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs., , , , , , and . ESSDERC, page 73-76. IEEE, (2012)SOI CMOS technology for quantum information processing., , , , , , , , , and 5 other author(s). ICICDT, page 1-4. IEEE, (2017)Back-gate effects and detailed characterization of junctionless transistor., , , , , , , and . ESSDERC, page 282-285. IEEE, (2015)Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs., , , , , , and . ESSDERC, page 300-303. IEEE, (2013)Analog performance of strained SOI nanowires down to 10K., , , , , , and . ESSDERC, page 222-225. IEEE, (2016)