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Disambiguation of "Pavanello, Marcelo Antonio"

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Analog performance of strained SOI nanowires down to 10K.

, , , , , , and . ESSDERC, page 222-225. IEEE, (2016)

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Antonio Raiolo University of Stuttgart

Giuliano Antonio Giacoppo University of Stuttgart

Rafael Antonio Lainez Reyes University of Stuttgart

Jesus Antonio Martinez Zarate University of Stuttgart

 

Other publications of authors with the same name

Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs., , , and . Microelectronics Reliability, 53 (6): 848-855 (2013)Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation., , , , and . Microelectronics Journal, 39 (12): 1663-1670 (2008)An explicit multi-exponential model for semiconductor junctions with series and shunt resistances., , , , , and . Microelectronics Reliability, 51 (12): 2044-2048 (2011)Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs., , , , and . SBCCI, page 26-. IEEE Computer Society, (2003)Evaluation of graded-channel SOI MOSFET operation at high temperatures., , and . Microelectronics Journal, 37 (7): 601-607 (2006)An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices., , , , and . Microelectronics Reliability, 52 (3): 519-524 (2012)Drain current model for short-channel triple gate junctionless nanowire transistors., , , , , , , and . Microelectronics Reliability, (2016)Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS., , , and . Microelectronics Journal, 37 (1): 31-37 (2006)Temperature dependence of the electrical characteristics up to 370 K of amorphous In-Ga-ZnO thin film transistors., , , , , , , and . Microelectronics Reliability, (2016)FOSS EKV2.6 Verilog-A Compact MOSFET Model., , , , , , , , , and 12 other author(s). ESSDERC, page 190-193. IEEE, (2019)