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Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models., , , , , , and . Microelectronics Journal, 44 (2): 80-85 (2013)Modeling the subthreshold region of OTFTs., , , and . CCE, page 1-4. IEEE, (2011)Drain current model for short-channel triple gate junctionless nanowire transistors., , , , , , , and . Microelectronics Reliability, (2016)Harmonic distortion analysis using an improved charge sheet model for PD SOI MOSFETs., , , and . Microelectronics Journal, 38 (3): 321-326 (2007)DC self-heating effects modelling in SOI and bulk FinFETs., , , , and . Microelectronics Journal, 46 (4): 320-326 (2015)Using Data Mining for Wine Quality Assessment., , , , , and . Discovery Science, volume 5808 of Lecture Notes in Computer Science, page 66-79. Springer, (2009)Determination of trap cross-section in a-Si: H p-i-n diodes parameters using simulation and parameter extraction., , , and . Microelectronics Reliability, 41 (4): 605-610 (2001)Characterization of MIS structures and PTFTs using TiOx deposited by spin-coating., , , , , , and . Microelectronics Reliability, 54 (5): 893-898 (2014)Effect of interface charge on the dc bias stress-induced deformation and shift of the transfer characteristic of amorphous oxide thin-film transistors., , and . Microelectronics Reliability, 52 (7): 1342-1345 (2012)Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation., , , , and . Microelectronics Journal, 39 (12): 1663-1670 (2008)