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Disambiguation of "Faynot, Olivier"

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Performance and reliability of strained SOI transistors for advanced planar FDSOI technology.

, , , , , , , , , and . IRPS, page 2. IEEE, (2015)

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Other publications of authors with the same name

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities., , , , , , , , , and 6 other author(s). ESSDERC, page 121-124. IEEE, (2012)Variability of planar Ultra-Thin Body and Buried oxide (UTBB) FDSOI MOSFETs., , , , , and . ICICDT, page 1-4. IEEE, (2014)Analog performance of strained SOI nanowires down to 10K., , , , , , and . ESSDERC, page 222-225. IEEE, (2016)CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits., , , , , , , and . ASP-DAC, page 336-343. IEEE, (2011)Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations., , , , , , , , , and 3 other author(s). ESSDERC, page 198-201. IEEE, (2013)Deep-amorphization and solid-phase epitaxial regrowth processes for hybrid orientation technologies in SOI MOSFETs with thin body., , , , , , , and . Microelectronics Reliability, 52 (11): 2602-2608 (2012)Performance and reliability of strained SOI transistors for advanced planar FDSOI technology., , , , , , , , , and . IRPS, page 2. IEEE, (2015)Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs., , , , , , , , and . IRPS, page 6. IEEE, (2018)A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool., , , , , , , , , and 6 other author(s). DATE, page 1192-1196. ACM, (2015)Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below., , , , , , , , , and . J. Low Power Electronics, 8 (1): 125-132 (2012)