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Disambiguation of "Billoint, Olivier"

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A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool.

, , , , , , , , , , , , , , , and . DATE, page 1192-1196. ACM, (2015)

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FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?, and . ISCAS, page 554-557. IEEE, (2013)A high-level design rule library addressing CMOS and heterogeneous technologies., , , , , , and . ICICDT, page 1-4. IEEE, (2014)Opportunities brought by sequential 3D CoolCube™ integration., , , , , , , , , and 11 other author(s). ESSDERC, page 226-229. IEEE, (2016)Compact interconnect approach for networks of neural cliques using 3D technology., , , , , , and . VLSI-SoC, page 116-121. IEEE, (2015)A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit., , , , , , , , and . ICICDT, page 141-144. IEEE, (2018)3DCoB: A new design approach for Monolithic 3D Integrated circuits., , , and . ASP-DAC, page 79-84. IEEE, (2014)Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes., , , , , , and . 3DIC, page 1-5. IEEE, (2016)Impact of intermediate BEOL technology on standard cell performances of 3D VLSI., , , , , , , , , and 3 other author(s). ESSDERC, page 218-221. IEEE, (2016)FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation., , , , , and . ReConFig, page 1-6. IEEE, (2013)From 2D to monolithic 3D predictive design platform: An innovative migration methodology for benchmark purpose., , , , , , , , and . 3DIC, page 1-5. IEEE, (2016)