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Compact interconnect approach for networks of neural cliques using 3D technology.

B. Boguslawski, H. Sarhan, F. Heitzmann, F. Seguin, S. Thuries, O. Billoint, and F. Clermidy. VLSI-SoC, page 116-121. IEEE, (2015)

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FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?J. Mäkipää, and O. Billoint. ISCAS, page 554-557. IEEE, (2013)A high-level design rule library addressing CMOS and heterogeneous technologies.G. Cibrario, M. Gary, F. Gays, K. Azizi-Mourier, O. Billoint, O. Turkyilmaz, and O. Rozeau. ICICDT, page 1-4. IEEE, (2014)Opportunities brought by sequential 3D CoolCube™ integration.M. Vinet, P. Batude, C. Fenouillet-Béranger, L. Brunet, V. Mazzocchi, C. Lu, F. Deprat, J. Micout, B. Previtali, P. Besombes and 11 other author(s). ESSDERC, page 226-229. IEEE, (2016)Compact interconnect approach for networks of neural cliques using 3D technology.B. Boguslawski, H. Sarhan, F. Heitzmann, F. Seguin, S. Thuries, O. Billoint, and F. Clermidy. VLSI-SoC, page 116-121. IEEE, (2015)A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit.F. Andrieu, P. Batude, L. Brunet, C. Fenouillet-Béranger, D. Lattard, S. Thuries, O. Billoint, R. Fournel, and M. Vinet. ICICDT, page 141-144. IEEE, (2018)3DCoB: A new design approach for Monolithic 3D Integrated circuits.H. Sarhan, S. Thuries, O. Billoint, and F. Clermidy. ASP-DAC, page 79-84. IEEE, (2014)Impact of intermediate BEOL technology on standard cell performances of 3D VLSI.M. Brocard, G. Berhault, S. Thuries, F. Clermidy, P. Batude, C. Fenouillet-Béranger, L. Brunet, F. Andrieu, F. Deprat, J. Lacord and 3 other author(s). ESSDERC, page 218-221. IEEE, (2016)Thermal performance of CoolCube™ monolithic and TSV-based 3D integration processes.C. Santos, P. Vivet, S. Thuries, O. Billoint, J. Colonna, P. Coudrain, and L. Wang. 3DIC, page 1-5. IEEE, (2016)FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation.C. Shan, E. Zianbetov, W. Yu, F. Anceau, O. Billoint, and D. Galayko. ReConFig, page 1-6. IEEE, (2013)An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits.H. Sarhan, S. Thuries, O. Billoint, and F. Clermidy. ISVLSI, page 350-355. IEEE Computer Society, (2015)

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Compact interconnect approach for networks of neural cliques using 3D technology.

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Disambiguation of "Billoint, Olivier"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Compact interconnect approach for networks of neural cliques using 3D technology.

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Compact interconnect approach for networks of neural cliques using 3D technology.