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Disambiguation of "Shan, Chuan"

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FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation.

, , , , , and . ReConFig, page 1-6. IEEE, (2013)

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Kerthana Shanmugam Dorairaj University of Stuttgart

Mirza Shan Fur University of Stuttgart

 

Other publications of authors with the same name

A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs., , , , and . NEWCAS, page 1-4. IEEE, (2015)Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology., , , , , , , , , and . IEEE Trans. on Circuits and Systems, 66-II (10): 1673-1677 (2019)Distributed clock generator for synchronous SoC using ADPLL network., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2013)On-chip clock error characterization for clock distribution system., , and . ISVLSI, page 102-108. IEEE Computer Socity, (2013)FPGA implementation of reconfigurable ADPLL network for distributed clock generation., , , , , , , , , and . FPT, page 1-4. IEEE, (2011)"Swimming pool"-like distributed architecture for clock generation in large many-core SoC., , , and . ISCAS, page 2768-2771. IEEE, (2014)Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks., , , , , and . NEWCAS, page 1-4. IEEE, (2016)Design and Modeling of ADPLL with sliding-window for wide range frequency tracking., , and . NEWCAS, page 269-272. IEEE, (2012)FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation., , , , , and . ReConFig, page 1-6. IEEE, (2013)A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC., , , , , , , and . Microelectronics Journal, 44 (9): 840-843 (2013)