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Guidelines for intermediate back end of line (BEOL) for 3D sequential integration., , , , , , , , , and 18 other author(s). ESSDERC, page 252-255. IEEE, (2017)Opportunities brought by sequential 3D CoolCube™ integration., , , , , , , , , and 11 other author(s). ESSDERC, page 226-229. IEEE, (2016)Recent advances in 3D VLSI integration., , , , , , , , , and 7 other author(s). ICICDT, page 1-4. IEEE, (2016)FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration., , , , , , , , , and 6 other author(s). ESSDERC, page 110-113. IEEE, (2014)Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells., , , , , , , , , and 2 other author(s). ISVLSI, page 539-544. IEEE Computer Society, (2017)Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices., , , , , , , , , and 5 other author(s). ESSDERC, page 144-147. IEEE, (2017)A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit., , , , , , , , and . ICICDT, page 141-144. IEEE, (2018)Impact of intermediate BEOL technology on standard cell performances of 3D VLSI., , , , , , , , , and 3 other author(s). ESSDERC, page 218-221. IEEE, (2016)