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Disambiguation of "Batude, Perrine"

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Guidelines for intermediate back end of line (BEOL) for 3D sequential integration.

, , , , , , , , , , , , , , , , , , , , , , , , , , , and . ESSDERC, page 252-255. IEEE, (2017)

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3D FPGA using high-density interconnect Monolithic Integration., , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Intermediate BEOL process influence on power and performance for 3DVLSI., , , , , , , and . 3DIC, page TS1.3.1-TS1.3.5. IEEE, (2015)Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices., , , , , , , , , and 5 other author(s). ESSDERC, page 144-147. IEEE, (2017)A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit., , , , , , , , and . ICICDT, page 141-144. IEEE, (2018)Impact of intermediate BEOL technology on standard cell performances of 3D VLSI., , , , , , , , , and 3 other author(s). ESSDERC, page 218-221. IEEE, (2016)Recent advances in 3D VLSI integration., , , , , , , , , and 7 other author(s). ICICDT, page 1-4. IEEE, (2016)Cell transformations and physical design techniques for 3D monolithic integrated circuits., , , , and . JETC, 9 (3): 19:1-19:28 (2013)From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges., , , , , , , , , and 2 other author(s). ISPD, page 127. ACM, (2015)Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges., , , , , , and . ICECS, page 157-160. IEEE, (2018)A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool., , , , , , , , , and 6 other author(s). DATE, page 1192-1196. ACM, (2015)