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Delay partitioning helps reducing variability in 3DVLSI., , , , and . ESSCIRC, page 75-78. IEEE, (2016)Recent advances in 3D VLSI integration., , , , , , , , , and 7 other author(s). ICICDT, page 1-4. IEEE, (2016)Piezoresistive transduction optimization of p-doped poly-Silicon NEMS., , , , , , , and . ESSDERC, page 149-152. IEEE, (2015)From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges., , , , , , , , , and 2 other author(s). ISPD, page 127. ACM, (2015)A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool., , , , , , , , , and 6 other author(s). DATE, page 1192-1196. ACM, (2015)Analog performance of strained SOI nanowires down to 10K., , , , , , and . ESSDERC, page 222-225. IEEE, (2016)Recent advances in 3D VLSI integration., , , , , , , , , and 7 other author(s). ICICDT, page 1-4. IEEE, (2016)Si MOS technology for spin-based quantum computing., , , , , , , , , and 7 other author(s). ESSDERC, page 12-17. IEEE, (2018)Towards a scalable quantum computer., , , , , , , and . DTIS, page 1. IEEE, (2018)FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration., , , , , , , , , and 6 other author(s). ESSDERC, page 110-113. IEEE, (2014)