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22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS.

Y. Tsunoda, T. Shibasaki, S. Ide, T. Mori, Y. Koyanagi, K. Tanaka, T. Ishihara, and H. Tamura. ISSCC, page 1-3. IEEE, (2015)

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22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS.T. Shibasaki, Y. Tsunoda, H. Oku, S. Ide, T. Mori, Y. Koyanagi, K. Tanaka, T. Ishihara, and H. Tamura. ISSCC, page 1-3. IEEE, (2015)A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers.R. Yuen, M. van Ierssel, A. Sheikholeslami, W. Walker, and H. Tamura. CICC, page 413-416. IEEE, (2006)A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.N. Nedovic, A. Kristensson, S. Parikh, S. Reddy, S. McLeod, N. Tzartzanis, K. Kanda, T. Yamamoto, S. Matsubara, M. Kibune and 13 other author(s). J. Solid-State Circuits, 45 (10): 2016-2029 (2010)A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX.N. Nedovic, N. Tzartzanis, H. Tamura, F. Rotella, M. Wiklund, Y. Mizutani, Y. Okaniwa, T. Kuroda, J. Ogawa, and W. Walker. J. Solid-State Circuits, 42 (12): 2726-2735 (2007)Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs.J. Liang, A. Sheikholeslami, H. Tamura, Y. Ogata, and H. Yamaguchi. J. Solid-State Circuits, 53 (9): 2696-2708 (2018)Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa and 2 other author(s). IEICE Transactions, 93-C (3): 295-302 (2010)18-GHz Clock Distribution Using a Coupled VCO Array.T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda. IEICE Transactions, 90-C (4): 811-822 (2007)A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS.B. Abiri, R. Shivnaraine, A. Sheikholeslami, H. Tamura, and M. Kibune. ISSCC, page 154-156. IEEE, (2011)A pattern-guided adaptive equalizer in 65nm CMOS.S. Shahramian, C. Ting, A. Sheikholeslami, H. Tamura, and M. Kibune. ISSCC, page 354-356. IEEE, (2011)A dynamic offset control technique for comparator design in scaled CMOS technology.X. Zhu, Y. Chen, M. Kibune, Y. Tomita, T. Hamada, H. Tamura, S. Tsukamoto, and T. Kuroda. CICC, page 495-498. IEEE, (2008)

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22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS.

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22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS.