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Disambiguation of "Shibasaki, Takayuki"

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22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS.

, , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS., , , , , , , , , and 13 other author(s). J. Solid-State Circuits, 45 (10): 2016-2029 (2010)A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS., , , , , , , , , and 8 other author(s). J. Solid-State Circuits, 44 (12): 3580-3589 (2009)22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS., , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS., , , , , , and . CICC, page 1-4. IEEE, (2010)A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range., , , , , , and . IEICE Transactions, 94-C (6): 1049-1052 (2011)A 30Gb/s 2x Half-Baud-Rate CDR., , , , , and . CICC, page 1-4. IEEE, (2019)18-GHz Clock Distribution Using a Coupled VCO Array., , , , , and . IEICE Transactions, 90-C (4): 811-822 (2007)A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (12): 3258-3267 (2013)