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Disambiguation of "Danjo, Takumi"

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A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.

, , , , , , , , , , and . J. Solid-State Circuits, 48 (12): 3258-3267 (2013)

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Other publications of authors with the same name

A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS., , , , and . VLSI-DAT, page 1-4. IEEE, (2012)Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC., , , , and . J. Solid-State Circuits, 50 (4): 932-945 (2015)7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique., , , , and . VLSIC, page 1-2. IEEE, (2014)A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)MLPerf™ HPC: A Holistic Benchmark Suite for Scientific Machine Learning on HPC Systems., , , , , , , , , and 33 other author(s). MLHPC@SC, page 33-45. IEEE, (2021)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 64-65. IEEE, (2016)A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (12): 3258-3267 (2013)A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS., , , , and . J. Solid-State Circuits, 49 (3): 673-682 (2014)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)