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A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.

Y. Doi, T. Shibasaki, T. Danjo, W. Chaivipas, T. Hashida, H. Miyaoka, M. Hoshino, Y. Koyanagi, T. Yamamoto, S. Tsukamoto, and H. Tamura. J. Solid-State Circuits, 48 (12): 3258-3267 (2013)

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Other publications of authors with the same name

An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration.T. Hashida, and M. Nagata. J. Solid-State Circuits, 46 (4): 789-796 (2011)A diagnosis testbench of analog IP cores against on-chip environmental disturbances.T. Hashida, Y. Araga, and M. Nagata. VTS, page 70-75. IEEE Computer Society, (2011)An on-chip waveform capturing technique pursuing minimum cost of integration.Y. Araga, T. Hashida, and M. Nagata. ISCAS, page 3557-3560. IEEE, (2010)Managing Non-Volatile Memory in Database Systems.A. van Renen, V. Leis, A. Kemper, T. Neumann, T. Hashida, K. Oe, Y. Doi, L. Harada, and M. Sato. SIGMOD Conference, page 1541-1555. ACM, (2018)A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.T. Hashida, Y. Tomita, Y. Ogata, K. Suzuki, S. Suzuki, T. Nakao, Y. Terao, S. Honda, S. Sakabayashi, R. Nishiyama and 6 other author(s). VLSIC, page 1-2. IEEE, (2014)A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength.T. Hashida, Y. Araga, and M. Nagata. IEICE Transactions, 94-C (6): 1016-1023 (2011)A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.Y. Doi, T. Shibasaki, T. Danjo, W. Chaivipas, T. Hashida, H. Miyaoka, M. Hoshino, Y. Koyanagi, T. Yamamoto, S. Tsukamoto and 1 other author(s). J. Solid-State Circuits, 48 (12): 3258-3267 (2013)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS.Y. Doi, T. Shibasaki, T. Danjo, W. Chaivipas, T. Hashida, H. Miyaoka, M. Hoshino, Y. Koyanagi, T. Yamamoto, S. Tsukamoto and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration.K. Noguchi, T. Hashida, and M. Nagata. IEICE Transactions, 90-C (6): 1189-1196 (2007)Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails.T. Hashida, and M. Nagata. IEICE Transactions, 93-C (6): 842-848 (2010)

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A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.

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A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.