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Disambiguation of "Tsukamoto, Sanroku"

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A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.

, , , , , , , , , , and . J. Solid-State Circuits, 48 (12): 3258-3267 (2013)

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Other publications of authors with the same name

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology., , , , , , , and . IEICE Transactions, 93-A (12): 2456-2462 (2010)A 10-b 50-MS/s 820- μ W SAR ADC With On-Chip Digital Calibration., , , and . IEEE Trans. Biomed. Circuits and Systems, 4 (6): 410-416 (2010)Split capacitor DAC mismatch calibration in successive approximation ADC., , , , , , , , , and 2 other author(s). CICC, page 279-282. IEEE, (2009)A 1 GHz CMOS comparator with dynamic offset control technique., , and . ASP-DAC, page 103-104. IEEE, (2009)A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration., , , and . IEICE Transactions, 95-C (6): 1026-1034 (2012)A dynamic offset control technique for comparator design in scaled CMOS technology., , , , , , , and . CICC, page 495-498. IEEE, (2008)A 7-bit 1-GS/s Flash ADC with Background Calibration., , and . IEICE Transactions, 97-C (4): 298-307 (2014)Advances in Analog-to-Digital Converters over the Last Decade.. IEICE Transactions, 100-A (2): 524-533 (2017)A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS., , and . IEICE Transactions, 93-A (12): 2600-2608 (2010)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)